| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 32.14 | 32.14 |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 14 | 4 | 28.57 |
| Total Bits | 28 | 9 | 32.14 |
| Total Bits 0->1 | 14 | 5 | 35.71 |
| Total Bits 1->0 | 14 | 4 | 28.57 |
| Ports | 12 | 2 | 16.67 |
| Port Bits | 24 | 5 | 20.83 |
| Port Bits 0->1 | 12 | 3 | 25.00 |
| Port Bits 1->0 | 12 | 2 | 16.67 |
| Signals | 2 | 2 | 100.00 |
| Signal Bits | 4 | 4 | 100.00 |
| Signal Bits 0->1 | 2 | 2 | 100.00 |
| Signal Bits 1->0 | 2 | 2 | 100.00 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| VDD | No | No | No | INPUT |
| VSS | No | No | No | INPUT |
| Q | No | No | No | OUTPUT |
| SO | No | No | No | OUTPUT |
| CK | Yes | Yes | Yes | INPUT |
| D | Yes | Yes | Yes | INPUT |
| SD | No | No | Yes | INPUT |
| SE | No | No | No | INPUT |
| RN | No | No | No | INPUT |
| CE | No | No | No | INPUT |
| SN | No | No | No | INPUT |
| notifier | No | No | No | INPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| CE_D | Yes | Yes | Yes |
| m | Yes | Yes | Yes |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |